This application claims priority to Japanese Patent Application No. 2005-007993, filed on Jan. 14, 2005.
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more specifically to a semiconductor device with a counter circuit.
2. Description of the Related Art
In a semiconductor device, a large number of circuit elements such as transistors, resistors, and capacitors are formed on a semiconductor substrate, and the circuit elements are connected to achieve a desired circuit operation and function. A counter circuit is a circuit used when a clock timer and an interval timer are formed.
FIG. 1 is a circuit diagram showing an arrangement of a conventional 3-bit synchronous type counter circuit. Referring now to FIG. 1, the conventional counter circuit is provided with flip-flops F10 to F12, an inverter circuit G1, an exclusive-OR gate circuit (will be referred to as “EXOR circuit” hereinafter) G2, and AND gate circuit G3, and another EXOR circuit G4.
A clock signal CLK is connected to clock input terminals C of the flip-flops F10 to F12. A reset signal RST is connected to reset terminals R of these flip-flops F10 to F12. An output terminal Q0 of the flip-flop F10 is connected to an external output terminal Q0, and connected via the inverter circuit G1 to a data input terminal D of the flip-flop F10. Also, the output terminal Q0 of the flip-flop F10 is connected to one input terminal of the EXOR circuit G2, and one input terminal of the AND gate circuit G3. An output terminal Q1 of the flip-flop F11 is connected to external output terminal Q1 and the other input terminal of the EXOR circuit G2. Also, the output terminal Q1 of he flip-flop F11 is connected to the other input terminal of the AND circuit G3. An output terminal of the EXOR circuit G2 is connected to the data input terminal D of the flip-flop F11. An output terminal Q2 of the flip-flop F12 is connected to an external output terminal Q2 and one input terminal of the EXOR circuit G4. Also, an output terminal of the AND gate circuit G3 is connected to the other input terminal of the EXOR circuit G4. An output terminal of the EXOR circuit G4 is connected to a data input terminal D of the flip-flop F12. As described above, the conventional synchronous type counter circuit shown in FIG. 1 is provided with the flip-flops F10 to F12 to which both of the clock signal CLK and the reset signal RST are supplied, the AND circuit G3 for carrying up the counter circuit, and the EXOR circuit G4.
Referring now to FIG. 2A to FIG. 2D, a description is made of operations as to the conventional synchronous type counter circuit shown in FIG. 1. First, the reset signal RST is supplied to the flip-flops F10 to F12, so that the outputs Q0 to Q2 of the flip-flops F10 to F12 are set to “0”, as shown in FIG. 2B to 2D. The output Q0 (=0) of the flip-flop F10 is inverted to “1” by the inverter circuit G1, and the value “1” is supplied to the data input terminal D of the flip-flop F10. The outputs Q0 and Q1 of the flip-flops F10 and F11 are “0”, and the EXOR circuit G2 supplies “0” to the data input terminal D of the flip-flop F11. Since the output Q0 and Q1 of the flip-flops F10 and F11 are “0”, the output of the AND gate circuit G3 becomes “0”. Also, the output Q2 of the flip-flop F12 is “0”. As a result, the EXOR circuit G4 supplies “0” to the data input terminal D of the flip-flop F12.
In this state, a first pulse of the clock signal CLK is supplied to the flip-flops F10 to F12, as shown in FIG. 2A. As a result, the output Q0 (=0) of the flip-flop F10 is changed into “1” in response to the pulse of the clock signal CLK, while the output Q1 of the flip-flop F11 and the output Q2 of the flip-flop F12 remain at “0”, as shown in FIG. 2B to FIG. 2D. The output Q0 of the flip-flop F10 is inverted by the inverter circuit G1, so that “0” is supplied to the data input terminal D of the flip-flop F10. Since the output Q1 of the flip-flop F10 is “1” and the output Q1 of the flip-flop F11 is “0”, the EXOR circuit G2 supplies “1” to the data input terminal D of the flip-flop F11. Also, since the output of the AND gate circuit G3 is “0” and the output Q2 of the flip-flop F12 is “0”, the EXOR circuit G4 supplies “0” to the data input terminal D of the flip-flop F12.
Next, as shown in FIG. 2A, a second pulse of the clock signal CLK is supplied to the flip-flops F10 to F12. As a result, as shown in FIG. 2B to FIG. 2D, in response to the second pulse of the clock signal CLK, the output Q0 of the flip-flop F10 is changed from “1” to “0”, the output Q1 of the flip-flop F11 is changed from “0” to “1”, and the output Q2 of the flip-flop F12 remains at “0”. The output Q0 of the flip-flop F10 is inverted by the inverter circuit G1, and the value “1” is supplied to the data input terminal D of the flip-flop F10. Since the output Q0 of the flip-flop F10 is “0” and the output Q1 of the flip-flop F11 is “1”, the EXOR circuit G2 supplies 1 “1” to the data input terminal D of the flip-flop F11. Also, since the output of the AND gate circuit G3 is “0”, and the output Q2 of the flip-flop F12 is “0”, the EXOR circuit G4 supplies “0” to the data input terminal D of the flip-flop F12.
Next, as shown in FIG. 2A, a third pulse of the clock signal CLK is supplied to the flip-flops F10 to F12. As a result, as shown in FIG. 2B to FIG. 2D, in response to this clock signal CLK, the output Q0 of the flip-flop F10 is changed from “0” to “1”, the output Q1 of the flip-flop F11 remains at “1”, and the output Q2 of the flip-flop F12 remains at “0”. The output Q0 of the flip-flop F10 is inverted by the inverter circuit G1, and “0” is supplied to the data input terminal D of the flip-flop F10. Since the output Q0 of the flip-flop F10 if “1” and the output Q1 of the flip-flop F11 is “1”, the EXOR circuit G2 supplies “0” to the data input terminal D of the flip-flop F11. Also, since the output of the AND gate circuit G3 is “1”, and the output Q2 of the flip-flop F12 is “0”, the EXOR circuit G4 supplies “1” to the data input terminal D of the flip-flop F12.
Next, as shown in FIG. 2A, a fourth pulse of the clock signal CLK is supplied to the flip-flops F10 to F12. As a result, as shown in FIG. 2B to FIG. 2D, in response to the fourth pulse of the clock signal CLK, the output Q0 of the flip-flop F10 is changed from “1” to “0”, the output Q1 of the flip-flop F11 is changed from “1” to “0”, and the output Q2 of the flip-flop F12 is changed from “0” to “1”. The output Q0 of the flip-flop F10 is inverted by the inverter circuit G1, and “1” is supplied to the data input terminal D of the flip-flop F10. Since the output Q0 of the flip-flop F10 is “0” and the output Q1 of the flip-flop F11 is “0”, the EXOR circuit G2 supplies “0” to the data input terminal D of the flip-flop F11. Also, since the output of the AND gate circuit G3 is “0”, and the output Q2 of the flip-flop F12 is “1”, the EXOR circuit G4 supplies “1” to the data input terminal D of the flip-flop F12.
Hereinafter, an operation similar to the above-described counting operation of the conventional counter circuit is repeatedly carried out every time a pulse of the clock signal CLK is supplied.
In this way, the flip-flop F10 divides the frequency of the clock signal CLK by “2”, the flip-flop F11 divides the frequency of the clock signal CLK by “4”, and the flip-flop F12 divides the frequency of the clock signal CLK by “8”.
However, in the counter circuit shown in FIG. 1, as shown in the timing chart of FIG. 2A to FIG. 2D, it is sufficient to the flip-flop F12 that the first one of the 4 pulses of the clock signal CLK is supplied to the flip-flop F12. However, the remaining 3 pulses are also supplied to the flip-flop F12. As a result, the flip-flop F12 operates by the three clock pulses in a useless manner, so that extra electric power is consumed.
Also, since an opportunity that the counter circuit operates in the extra manner increases, there a great possibility that noise is generated due to slight fluctuation in current and voltage in circuit elements themselves. Also, in order to suppress power consumption, an asynchronous type counter circuit may be satisfactorily used. Such an asynchronous type counter circuit is not suitably used in case that a delay with reference to a reference clock is large, a correct clock generation such as a times is required, and the counter circuit is used in a high-speed operation.
Another conventional counter is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-303738). In this conventional counter, an external setting value indicative of a counting end value is divided into an upper bit portion and a lower bit portion. A first counter circuit is used for the lower bit portion, whereas a second counter circuit with a small circuit scale and small power consumption is used for the upper bit portion. The first circuit unit counts a high frequency clock, and a clock obtained by frequency-dividing the high frequency clock is supplied to the second counter circuit.